Peripheral Component Interconnect (PCI)

The Peripheral Component Interconnect, or PCI Local Bus (commonly PCI), specifies a computer bus for attaching peripheral devices to a computer motherboard. These devices can take any one of the following forms:

• An integrated circuit fitted onto the motherboard itself, called a planar device in the PCI specification.
• An expansion card that fits into a socket.

The PCI bus is common in modern PCs, where it has displaced ISA and VESA Local Bus as the standard expansion bus, but it also appears in many other computer types. The bus is being succeeded by PCI Express, which launched in 2004 and offers much higher bandwidth. As of 2007 the PCI standard is still used by many legacy and new devices that do not require the higher bandwidth of PCI-E. New computers are also still provided with sample PCI slots.

The PCI specification covers the physical size of the bus (including wire spacing), electrical characteristics, bus timing, and protocols. The specification can be purchased from the PCI Special Interest Group (PCI-SIG).

Typical PCI cards used in PCs include: network cards, sound cards, modems, extra ports such as USB or serial, TV tuner cards and disk controllers. Historically video cards were typically PCI devices, but growing bandwidth requirements soon outgrew the capabilities of PCI. Today PCI video cards are uncommon and principally at the lower end of the market. However, the advent of Windows Vista with its strenuous requirements for its Aero interface, combined with many PCs lacking AGP or PCI Express slots, means that there are now many "Vista Ready" PCI graphics cards released , with a claim by one manufacturer that "In fact, what we have experienced is growing demand for PCI graphics upgrades, because the PCI card works in all PCs…Past, Present and Future."At Computex 2008, a number of cutting-edge GeForce 8 based cards were released.

Many devices traditionally provided on expansion cards are now commonly integrated onto the motherboard itself, meaning that modern PCs often have no cards fitted. However, PCI is still used for certain specialized cards, although many tasks traditionally performed by expansion cards may now be performed equally well by USB devices.

Work on PCI began at Intel's Architecture Lab circa 1990. PCI 1.0, which was merely a component-level specification, was released on June 22, 1992. PCI 2.0, which was the first to establish standards for the connector and motherboard slot, was released on April 30, 1993. PCI 2.1 was released on June 1, 1995.

PCI was immediately put to use in servers, replacing MCA and EISA as the server expansion bus of choice. In mainstream PCs, PCI was slower to replace VESA Local Bus (VLB), and did not gain significant market penetration until late 1994 in second-generation Pentium PCs. By 1996 VLB was all but extinct, and manufacturers had adopted PCI even for 486 computers. EISA continued to be used alongside PCI through 2000. Apple Computer adopted PCI for professional Power Macintosh computers (replacing NuBus) in mid-1995, and the consumer Performa product line (replacing LC PDS) in mid-1996.

Later revisions of PCI added new features and performance improvements, including a 66 MHz 3.3 V standard and 133 MHz PCI-X, and the adaptation of PCI signaling to other form factors. Both PCI-X 1.0b and PCI-X 2.0 are backward compatible with some PCI standards. With the introduction of the serial PCI Express standard in 2004, motherboard manufacturers have included progressively fewer PCI expansion slots in favor of the new standard. Although it is still common to see both interfaces implemented side-by-side, traditional PCI is likely to slowly die out in coming years.

PCI provides two separate 32-bit or 64-bit address spaces corresponding to the memory and I/O port address spaces of the x86 processor family. Addresses in these address spaces are assigned by software. A third address space, called the PCI Configuration Space, which uses a fixed addressing scheme, allows software to determine the amount of memory and I/O address space needed by each device. Each device can request up to six areas of memory space or I/O port space via its configuration space registers.

In a typical system, the firmware (or operating system) queries all PCI buses at startup time (via PCI Configuration Space) to find out what devices are present and what system resources (memory space, I/O space, interrupt lines, etc.) each needs. It then allocates the resources and tells each device what its allocation is.

The PCI configuration space also contains a small amount of device type information, which helps an operating system choose device drivers for it, or at least to have a dialogue with a user about the system configuration.

Devices may have an on-board ROM containing executable code for x86 or PA-RISC processors, an Open Firmware driver, or an EFI driver. These are typically necessary for devices used during system startup, before device drivers are loaded by the operating system.

In addition there are PCI Latency Timers that are a mechanism for PCI Bus-Mastering devices to share the PCI bus fairly. "Fair" in this case means that devices won't use such a large portion of the available PCI bus bandwidth that other devices aren't able to get needed work done. Note, this does not apply to PCIE.

"How this works is that each PCI device that can operate in bus-master mode is required to implement a timer, called the Latency Timer, that limits the time that device can hold the PCI bus. The timer starts when the device gains bus ownership, and counts down at the rate of the PCI clock. When the counter reaches zero, the device is required to release the bus. If no other devices are waiting for bus ownership, it may simply grab the bus again and transfer more data."

There is a PCI Latency Tool available, you can use a search engine to locate the latest version. This tool will allow you to change/set the latency for any PCI card that allows it. These specifications represent the most common version of PCI used in normal PCs.

• 33.33 MHz clock with synchronous transfers
• peak transfer rate of 133 MB/s (133 million bytes per second) for 32-bit bus width (33.33 MHz × 32 bits ÷ 8 bits/byte = 133 MB/s)
• peak transfer rate of 266 MB/s for 64-bit bus width
• 32-bit or 64-bit bus width
• 32-bit address space (4 gigabytes)
• 32-bit I/O port space
• 256-byte configuration space
• 5-volt signaling
• reflected-wave switching

Data and source mostly taken from Wikipedia.